One method of providing a delay or of timing an event using an integrated circuit (IC) chip is shown in FIG. 5, in which power supply system 500 is shown on a circuit board 502. Power supply system 500 includes an IC chip 504 that can be, for example, a load switch or a low-dropout (LDO) regulator. IC chip 504 is coupled to an input voltage Vin through pin Pa and provides an output voltage Vout through pin Pb. Although not specifically shown in this figure, a power transistor is coupled between input voltage Vin and output voltage Vout to control when a current is allowed to flow.
IC chip 504 contains a timing circuit 506, which is coupled to an external capacitor C1 through pin Pc. Timing circuit 506 is coupled to pin Pc in order to use an external capacitor C1 to time an event. For example, when a fault condition such as a short occurs at a load to which power supply system 500 is coupled, IC chip 504 may need to be turned off and then on to reset the IC chip. Typically, it is desirable for a given time period to elapse between the time IC chip 504 is turned off and when IC chip 504 is turned back on. Timing of the given time period can be provided by charging external capacitor C1 at a constant rate, e.g., using a current source, and detecting when external capacitor C1 has reached a threshold voltage that represents the expected time period.
When a large current is needed on Vout, two or more copies of IC chip 504 can be coupled in parallel between input voltage Vin and output voltage Vout in order to increase the current-carrying capabilities of the system. It will be recognized that when multiple IC chips 504 are coupled in parallel, the IC chips need to act synchronously whenever they are switched on or off. When the switching occurs due to a fault condition, synchronous action can be accomplished by coupling a respective timing circuit 506 from each IC chip 504 to external capacitor C1; each IC chip can help charge external capacitor C1 and can monitor the voltage on external capacitor C1. However, when combining existing IC chips in such a manner, unexpected issues can occur and cause the system to lose synchronization.